Frame synchronizing signal detecting method for reducing occurrence of error synchronization before link of frame synchronizing signal is established

ABSTRACT

A frame synchronizing signal detecting method according to the invention is used in a data multiplexing transmitter-receiver which is provided with a transmitter-receiver that transmits and receives at least a radio-frequency signal, a modulator-demodulator that converts the radio-frequency signal to a baseband signal and vice versa and a baseband signal processor that processes the baseband signal and in which the baseband signal processor is provided with a frame synchronizing signal detector, and when a frame synchronizing signal included in received data is detected, the frame synchronizing signal detector sets the detection precision of the frame synchronizing signal before a frame synchronization link is established to a value higher than regular detection precision and sets the detection precision of the frame synchronizing signal after the frame synchronization link is established to a value lower than the regular detection precision.

This application claims the benefit of priority to Japanese PatentApplication No. 2001-033992, herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a frame synchronizing signal (a uniqueword) detecting method, particularly relates to a frame synchronizingsignal detecting method used for a data multiplexingtransmitter-receiver of achieving the stable establishment of a link byenhancing the detection precision of a frame synchronizing signal beforethe link of a frame synchronizing signal is established and ofpreventing non-detection due to noise and disturbance by lowering thedetection precision of a frame synchronizing signal after the link of aframe synchronizing signal is established.

2. Description of the Related Art

Generally, a frame synchronizing signal (also called a unique word or aflag) having a specific bit pattern is added to the head of dataincluded in each data packet, when a data multiplexingtransmitter-receiver at the transmitting end transmits data, ittransmits the data of which a frame synchronizing signal is added to thehead of the data string, when another data multiplexingtransmitter-receiver at the receiving end receives the transmitted data,it detects the frame synchronizing signal added to the data and framesynchronization with the data multiplexing transmitter-receiver at thetransmitting end is achieved using the detected frame synchronizingsignal.

A frame synchronizing signal is normally detected by a framesynchronizing signal detector provided to a baseband signal processor ina data multiplexing transmitter-receiver. In this case, when the framesynchronizing signal detector receives data, it searches a framesynchronizing signal having a specific bit pattern in the received data,when the added position of the frame synchronizing signal in a frame isverified by the search, a frame synchronization link is established andafterward, the frame synchronizing signal is extracted based upon theverified added position of the frame synchronizing signal.

FIG. 2 is a block diagram showing one example of the configuration ofthe main part of a known data multiplexing transmitter-receiver.

As shown in FIG. 2, a data multiplexing transmitter-receiver 20 isprovided with an antenna 21, a duplexer 22 formed by a change-overswitch, a radio-frequency (RF) transmitter-receiver 23 provided with aradio-frequency (RF) signal transmitter 23 ₁ and a radio-frequency (RF)signal receiver 23 ₂, a modulator-demodulator (MODEM) 24 provided with amodulating circuit (MOD) 24 ₁ that converts a baseband signal to aradio-frequency signal and a demodulating circuit (DEM) 24 ₂ thatconverts a radio-frequency signal to a baseband signal and a framesynchronizing signal detector 25 ₁, includes a baseband signal processor25 that processes a baseband signal, a control panel 26 and amicrocomputer and also includes a control unit (CPU) 27 that generallycontrols the data multiplexing transmitter-receiver 20.

The common terminal of the duplexer 22 is connected to the antenna 21,one selection terminal is connected to the output terminal of theradio-frequency signal transmitter 23 ₁, the other selection terminal isconnected to the input terminal of the radio-frequency signal receiver23 ₂ and the control terminal is connected to the control unit 27. Theinput terminal of the modulating circuit 24 ₁ is connected to the outputterminal of the baseband signal processor 25 and the output terminal isconnected to the input terminal of the radio-frequency signaltransmitter 23 ₁. The input terminal of the demodulating circuit 24 ₂ isconnected to the output terminal of the radio-frequency signal receiver23 ₂ and the output terminal is connected to the input terminal of thebaseband signal processor 25. The baseband signal processor 25 isconnected to the control unit 27 and the control panel 26 is alsoconnected to the control unit 27.

The data multiplexing transmitter-receiver 20 having the configurationdescribed above operates as follows.

Data transmission between the data multiplexing transmitter-receiver 20and a data multiplexing transmitter-receiver on the side of acounterpart (not shown) is set so that the transmitting timing oftransmit data and the receiving timing of receive data alternatelypresent themselves by time division multiplexing.

When the data multiplexing transmitter-receiver 20 comes into datatransmitting timing, the control unit 27 instructs the baseband signalprocessor 25 to generate transmit data and switches the duplexer 22 tothe side of the radio-frequency signal transmitter 23 ₁. At this time,the baseband signal processor 25 generates packet data of a determinedformat and supplies the packet data to the modulating circuit 24 ₁. Themodulating circuit 24 ₁ modulates the supplied packet data to atransmitting radio-frequency signal and supplies it to theradio-frequency signal transmitter 23 ₁. The radio-frequency signaltransmitter 23 ₁ amplifies the supplied transmitting radio-frequencysignal so that the level reaches a transmission level, supplies it tothe antenna 21 via the already switched duplexer 22 and transmits it tothe data multiplexing transmitter-receiver on the side of thecounterpart in a transmitting timing as a radio signal.

In the meantime, when the data multiplexing transmitter-receiver 20comes into data receiving timing, the control unit 27 instructs thebaseband signal processor 25 to prepare for the processing of receivedata and switches the duplexer 22 to the side of the radio-frequencysignal receiver 23 ₂. At this time, when a radio signal includingreceive data is incoming to the antenna 21, the radio-frequency signalreceiver 23 ₂ receives the radio signal as a radio-frequency signal forreceiving from the antenna 21 via the already switched duplexer 22,amplifies the radio-frequency signal for receiving to a predeterminedlevel and supplies it to the demodulating circuit 24 ₂. The demodulatingcircuit 24 ₂ demodulates the supplied radio-frequency signal forreceiving to a baseband signal and generates packet data. The packetdata is supplied to the baseband signal processor 25 and after it ischecked whether the packet data is normal receive data or not by thebaseband signal processor 25, data is extracted and is supplied to thecontrol unit 27 and others. When the frame synchronizing signal detector25 ₁ in the baseband signal processor 25 receives data, it searches aframe synchronizing signal having a specific bit pattern in the receiveddata as described above, when the added position of the framesynchronizing signal in the data is verified in the search, a framesynchronization link is established, afterward, the frame synchronizingsignal is extracted based upon the verified added position of the framesynchronizing signal and the extracted frame synchronizing signal issupplied to the control unit 27 and others.

Afterward, when the data multiplexing transmitter-receiver 20 comes intodata transmitting timing, the same processing as that at thetransmitting timing is executed again and afterward, receiving data andtransmitting data are also repeatedly executed.

The known data multiplexing transmitter-receiver 20 sets the detectionprecision of a frame synchronizing signal to detection precisionexperientially determined (regular detection precision) when the framesynchronizing signal is detected by the frame synchronizing signaldetector 25 ₁and establishes a frame synchronizing signal link dependingupon the set regular detection precision.

The reason why the detection precision of a frame synchronizing signalis set to such regular detection precision is as follows. If thedetection precision of a frame synchronizing signal is set so that it ishigher than the regular detection precision, there is an advantage inthat error synchronization is reduced and the establishment of a stablelink can be achieved before a frame synchronizing signal link isestablished (a link is tried), however, there is a disadvantage in thatafter a frame synchronizing signal link is established, non-detectiondue to slight noise superimposed on data and disturbance is often causedand the detection rate of a frame synchronizing signal is deteriorated.In the meantime, if the detection precision of a frame synchronizingsignal is set so that it is lower than the regular detection precision,there is an advantage in that the occurrence of non-detection due toslight noise superimposed on data and disturbance is reduced and thedetection rate of a frame synchronizing signal is enhanced after a framesynchronizing signal link is established, however, there is adisadvantage in that before a frame synchronizing signal link isestablished, error synchronization is frequently caused and it takes along time to establish a link.

The regular detection precision used in the known data multiplexingtransmitter-receiver 20 when a frame synchronizing signal is detected isacquired as a result by relieving the disadvantage in the case where thedetection precision of a frame synchronizing signal is set so that it ishigher than the regular detection precision and the disadvantage in thecase where the detection precision of a frame synchronizing signal isset so that it is lower than the regular detection precision, however,these disadvantages are not completely solved.

SUMMARY OF THE INVENTION

The invention is made in view of such a technical background and theobject is to provide a frame synchronizing signal detecting method ofreducing error synchronization before a frame synchronizing signal linkis established and of enhancing the detection rate of a framesynchronizing signal after a frame synchronizing signal link isestablished.

To achieve the object, the frame synchronizing signal detecting methodaccording to the invention is characterized in that atransmitter-receiver that transmits and receives a radio-frequencysignal, a modulator-demodulator that converts a radio-frequency signalto a baseband signal and converts vice versa and a baseband signalprocessor that processes a baseband signal are at least provided, thebaseband signal processor is provided with a frame synchronizing signaldetector and when a frame synchronizing signal included in received datais detected the frame synchronizing signal detector sets the detectionprecision of a frame synchronizing signal before a frame synchronizationlink is established to a high value and sets the detection precision ofa frame synchronizing signal after the frame synchronization link isestablished to a lower value than the abovementioned detectionprecision.

According to the means, the occurrence of error synchronization isreduced and the establishment of a stable link can be achieved bysetting the detection precision of a frame synchronizing signal before aframe synchronization link is established so that it is high andnon-detection due to slight noise superimposed on data and disturbanceis reduced and the detection rate of a frame synchronizing signal can beenhanced by setting the detection precision of a frame synchronizingsignal after a frame synchronization link is established so that it islow.

As an example suitable for the means, the frame synchronizing signaldetector is provided with a shift register that temporarily storesreceived data, a frame synchronizing signal storage that stores a framesynchronizing signal, a comparator that detects coincidence of a framesynchronizing signal extracted from the shift register and the framesynchronizing signal output from the frame synchronizing signal storage,a counter that counts the coincidence output of the comparator, adetection precision setting device that sets the detection precision ofthe frame synchronizing signal to a high value or a low value accordingto the value of the counter so that it is high or low and a framesynchronizing signal detection signal output device that detects theframe synchronizing signal from the received data with the detectionprecision set by the detection precision setting device.

According to the configuration, if a function produced by theabovementioned means is achieved by the frame synchronizing signaldetector, the frame synchronizing signal detector can have a relativelysimple configuration and as a result, the manufacturing cost and theoccupied volume are not greatly increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows one embodiment of a frame synchronizing signal detectingmethod according to the invention and is a block diagram showing theconfiguration of the main part of a frame synchronizing signal detectorin a baseband signal processor of a data multiplexingtransmitter-receiver; and

FIG. 2 is a block diagram showing one example of the configuration ofthe main part of a known data multiplexing transmitter-receiver.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the drawings, an embodiment of the invention will bedescribed below.

FIG. 1 shows one embodiment of a frame synchronizing signal detectingmethod according to the invention and is a block diagram showing theconfiguration of the main part of a frame synchronizing signal detectorin a baseband signal processor of a data multiplexingtransmitter-receiver.

As shown in FIG. 1, as components except the baseband signal processorin the data multiplexing transmitter-receiver are substantially the sameas those in a known data multiplexing transmitter-receiver shown in FIG.2, they are not shown in FIG. 1.

As shown in FIG. 1, the frame synchronizing signal detector 1 ₁ in thebaseband signal processor 1 includes a shift register (SR) 2 composed ofm (an integer) rows the number of which is equal to a sampling rate (thenumber of data shift clocks) and n (an integer) columns for sequentiallyshifting received data, a comparator (COMP) 3 that detects the number ofcoincidence between a bit input from the shift register 2 and a bitinput from a frame synchronizing signal storage 4 described later andgenerates incidence output every time, the frame synchronizing signalstorage 4 that stores a frame synchronizing signal having a specific bitpattern, for example ‘01111110’, a coincidence number counter 5 thatcounts the number of coincidence output supplied from the comparator 3for every frame, a detection precision setting device 6 that selectshigh detection precision or low detection precision according to thenumber of counts supplied from the coincidence number counter 5 and setsthe detection precision of a frame synchronizing signal output from aframe synchronizing signal detection signal output device 7 describedlater and the frame synchronizing signal detection signal output device7 that detects a frame synchronizing signal in the received dataaccording to detection precision setting information supplied from thedetection precision setting device 6 and supplies the detected framesynchronizing signal to a frame synchronizing signal detection signaloutput terminal 8. Bit data D₀₀ and D_((n−1)0) in “D₀₀, D₀₁, - - - ,D_(0(m−1)), D₁₀, D₁₁, - - - , D_(1(m−1)), - - - , D_((n−1)0),D_((n−1)1), - - - , D_((n−1) (m−1))” show data bits included in each rowof the shift register 2.

In the frame synchronizing signal detector 1 ₁, the input terminal ofthe shift register 2 is connected to the output terminal of ademodulating circuit located before and not shown in FIG. 1 and theoutput terminal is connected to a first input terminal of the comparator3. A second input terminal of the comparator 3 is connected to theoutput terminal of the frame synchronizing signal storage 4 and theoutput terminal is connected to the input terminal of the coincidencenumber counter 5. The output terminal of the coincidence number counter5 is connected to the input terminal of the frame synchronizing signaldetection signal output device 7. The control terminal of the framesynchronizing signal detection signal output device 7 is connected tothe output terminal of the detection precision setting device 6 and theoutput terminal of the coincidence number counter 5 and the outputterminal is connected to the frame synchronizing signal detection signaloutput terminal 8.

The frame synchronizing signal detector 1 ₁ having the abovementionedconfiguration is operated as follows.

First, the operation in link trial, that is, the operation until a framesynchronization link is established will be described.

When received data is supplied from the demodulating circuit locatedbefore to the frame synchronizing signal detector 1 ₁, the received datais sampled at a rate equivalent to m times of the transfer rate of thereceived data by a shift clock signal and is sequentially accommodatedin the shift register 2. At this time, the comparator 3 sequentiallycompares a bit pattern sequentially output from the output terminal ofthe shift register 2 and the specific bit pattern of the framesynchronizing signal sequentially output from the frame synchronizingsignal storage 4 for every bit, generates one polarity of, for example,positive coincidence output when the bits are coincident in thecomparison of the bits and generates the other polarity of, for example,inequality output at a zero level when the bits are not coincident.Next, the coincidence number counter 5 counts the number of coincidentoutput for every frame of the received data and supplies the number ofcounts to the frame synchronizing signal detection signal output device7. As the added position of a frame synchronizing signal is not verifiedbefore a frame synchronization link is established, the detectionprecision setting device 6 supplies a signal set so that a framesynchronizing signal is detected with detection precision higher thanregular detection precision to the frame synchronizing signal detectionsignal output device 7. At this time, in the frame synchronizing signaldetection signal output device 7, the detection precision of a framesynchronizing signal is set to detection precision higher than theregular detection precision, a frame synchronizing signal in thereceived data is detected with the higher detection precision, as aresult, the added position of the frame synchronizing signal is verifiedand a frame synchronization link is established.

Next, the operation after the frame synchronization link is establishedwill be described.

This case is identical to the abovementioned case in that when receiveddata is supplied from the demodulating circuit located before to theframe synchronizing signal detector 1 ₁, the received data is sampled ata rate equivalent to m times of the transfer rate of the received databy a shift clock signal and is sequentially accommodated in the shiftregister 2. At this time, as a frame synchronization link is establishedand the added position of a frame synchronizing signal can be verified,the comparator 3 sequentially compares a bit pattern from the outputterminal of the shift register 2 and the specific bit patternsequentially output from the frame synchronizing signal storage 4 forevery bit at timing at which a data bit in the verified added positionof the frame synchronizing signal is sequentially output from the outputterminal of the shift register 2, as in the abovementioned case, whenthe bits are coincident in the comparison of the bits, the comparatorgenerates one polarity of, for example positive coincidence output andwhen the bits are not coincident, the comparator generates the otherpolarity of, for example, inequality output at a zero level. Next, thecoincidence number counter 5 counts the number of coincidence output forevery frame of the received data and supplies the number of counts tothe detection precision setting device 6. The detection precisionsetting device 6 supplies a signal set so that a frame synchronizingsignal is detected with detection precision lower than the regulardetection precision to the frame synchronizing signal detection signaloutput device 7 because the frame synchronization link is established.At this time, in the frame synchronizing signal detection signal outputdevice 7, the detection precision of a frame synchronizing signal is setto detection precision lower than the regular detection precision, aframe synchronizing signal in the received data is detected with thelower detection precision and the detected frame synchronizing signal issupplied to a control unit not shown in FIG. 1 and others.

The detection precision higher than the regular detection precision inthis embodiment means that in the case where the number m of the rows ofthe shift register is 12, a bit pattern of a frame synchronizing signalin the received data and the specific bit pattern of the framesynchronizing signal stored in the frame synchronizing signal storage 4are coincident during six or more continuous clock pulses and in themeantime, the detection precision lower than the regular detectionprecision means that in the case where the number m of the rows of theshift register is 12, a bit pattern of a frame synchronizing signal inthe received data and the specific bit pattern of the framesynchronizing signal stored in the frame synchronizing signal storage 4are coincident during three continuous clock pulses or approximately 3continuous clock pulses.

As described above, in this embodiment, as the detection precision of aframe synchronizing signal before a frame synchronization link isestablished is set to a higher value than the regular detectionprecision and in the meantime, the detection precision of the framesynchronizing signal after the frame synchronization link is establishedis set to a lower value than the regular detection precision, theestablishment of a stable link in which error synchronization is reducedis achieved before the frame synchronization link is established,undetection due to slight noise superimposed on data and disturbance isprevented after the frame synchronization link is established and theratio of the detection of a frame synchronizing signal is enhanced.

1. A frame synchronizing signal detecting method, wherein the method isused in a data multiplexing transmitter-receiver which is provided witha transmitter-receiver that transmits and receives at least aradio-frequency signal, a modulator-demodulator that coverts theradio-frequency signal to a baseband signal and converts the basebandsignal to the radio-frequency signal and a baseband signal processorthat processes the baseband signal and in which the baseband signalprocessor is provided with a frame synchronizing signal detector,wherein when a frame synchronizing signal included in received data isdetected, the frame synchronizing signal detector sets a detectionprecision of the frame synchronizing signal before a framesynchronization link is established to a high value and sets thedetection precision of the frame synchronizing signal after the framesynchronization link is established to a lower value than the highvalue, and wherein the frame synchronizing signal detector is providedwith a shift register that temporarily stores received data, a framesynchronizing signal storage that stores a frame synchronizing signal, acomparator that detects coincidence of the frame synchronizing signalextracted from the shift register and the frame synchronizing signaloutput from the frame synchronizing signal storage, a counter thatcounts a coincidence output of the comparator, a detection precisionsetting device that sets the detection precision of the framesynchronizing signal to one of the high value and the low valueaccording to a value of the counter and a frame synchronizing signaldetection signal output device that detects a frame synchronizing signalfrom the received data with detection precision set by the detectionprecision setting device.